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9-6
Error Detection Registers
SV51011
2014.01.10
Error Detection Registers
This section describes the registers used in user mode.
Figure 9-3: Block Diagram for Error Detection in User Mode
The block diagram shows the registers and data flow in user mode.
32-bit Error Detection
Readback
Bitstream with
Expected CRC
Error
Detection
Control
CRC Calculation, Error
Search Engine, and
Internal Scrubbing
Syndrome
Register
State
Machine
Signals
Error
Error Injection
Block
JTAG
Message
Register
User
CRC_ERROR
Fault
Injection
Register
JTAG
Fault
Injection
Register
Table 9-5: Error Detection Registers
Update
Register
JTAG
Shift
Register
JTAG TDO
Update
Register
User
Shift
Register
General Routing
Name
Syndrome register
Error message register (EMR)
JTAG update register
JTAG shift register
Altera Corporation
Width (Bits)
32
67
67
67
Description
Contains the 32-bit CRC signature calculated for the current
frame. If the CRC value is 0, the CRC_ERROR pin is driven
low to indicate no error. Otherwise, the pin is pulled high.
Contains error details for single-bit and double-adjacent
errors. The error detection circuitry updates this register
each time the circuitry detects an error. Figure 9-4 shows
the fields in this register and Table 9-6 lists the possible error
types.
This register is automatically updated with the contents of
the EMR one clock cycle after the content of this register is
validated. The JTAG update register includes a clock enable,
which must be asserted before its contents are written to the
JTAG shift register. This requirement ensures that the JTAG
update register is not overwritten when its contents are being
read by the JTAG shift register.
This register allows you to access the contents of the JTAG
update register via the JTAG interface using the SHIFT_
EDERROR_REG JTAG instruction.
SEU Mitigation for Stratix V Devices
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